Various input/output (I/O) interfaces of digital integrated circuits use a PLL as a frequency synthesizer and also as a noise filter. A typical PLL includes a phase/frequency detector and a closed loop feedback divider. The feedback divider has a particular set of divider values based on a desired PLL output clock signal frequency. The phase-frequency detector compares the phase of a reference signal to an internal PLL feedback signal, and outputs a signal to adjust the frequency of the PLL clock output signal in a direction that eliminates the phase difference between the two signals. When the phase and frequency of the reference signal and the PLL clock output signal are aligned, the PLL output signal is “locked” to the reference signal.
As integrated circuits continue to operate with increasing data rates, the specifications of the associated PLLs become increasingly difficult to meet. For example, an amount of jitter that is allowed to propagate from the reference signal to the PLL output clock signal is one such specification. In particular, the amount of phase shift produced as a result of power supply noise, substrate noise, and capacitor loading, is directly related to how quickly the PLL can lock and correct the output frequency. Since the phase or frequency error is based on the operating frequency divided by the loop bandwidth, errors can be accumulated for a number of cycles. To compensate, some PLLs are implemented to position the loop bandwidth as close as possible to the reference frequency bandwidth. However, conservatively setting the bandwidth of a PLL generally corresponds to the PLL performing slow phase and frequency lock resulting in poor jitter performance over process, voltage, and temperature variations.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.